看下这个例程

问题1：用版本v0.3.2 的函数psram_init 初始化不通过 但是使用v0.2.3中的psram_init 替换后能正常初始化 且测试数据正常
相关代码：

//前提 main.c 内初始时钟（hw_clock_init）正常 否则(psram_init)会一直卡在初始化中 
//相关时钟初始如下： 
__RAM_CODE void hw_clock_init(void)
{
    
#if 0
	System_ClkConfig_t sys_clk_cfg;
    sys_clk_cfg.SPLL_CFG.PLL_N = 8;
    sys_clk_cfg.SPLL_CFG.PLL_M = 0;
    sys_clk_cfg.SPLL_CFG.PowerEn = 1;
    sys_clk_cfg.MCU_Clock_Source = MCU_CLK_SEL_SPLL_CLK;
    sys_clk_cfg.SOC_DIV = 1;
    sys_clk_cfg.MCU_DIV = 1;
    sys_clk_cfg.APB0_DIV = 1;
    sys_clk_cfg.APB1_DIV = 1;
    sys_clk_cfg.APB2_DIV = 1;
 
    System_SPLL_config(&sys_clk_cfg.SPLL_CFG, 1000);
    System_MCU_clock_Config(&sys_clk_cfg);
	
#else
    System_ClkConfig_t ClkConfig;
    /* CORE HSCLK Config */
    ClkConfig.CORE_HSCLK_CFG.CORE_HSCLK_Source = CORE_HSCLK_SEL_HES;
    /* PLL clock = HSE_VALUE*N + (HSE_VALUE/65535)*M */
    /* SPLL CLK Config */
    ClkConfig.SPLL_CFG.PowerEn = PLL_POWER_ENABLE;
    ClkConfig.SPLL_CFG.PLL_N = 9;
    ClkConfig.SPLL_CFG.PLL_M = 0;
    /* PLL clock = HSE_VALUE*N + (HSE_VALUE/65535)*M */
    /* AUPLL CLK Config */
    ClkConfig.AUPLL_CFG.PowerEn = PLL_POWER_ENABLE;
    ClkConfig.AUPLL_CFG.PLL_N = 8;
    ClkConfig.AUPLL_CFG.PLL_K = 0;
    ClkConfig.AUPLL_CFG.PLL_D = 0;    
    System_CORE_HSCLK_config(&ClkConfig.CORE_HSCLK_CFG);
    if (System_SPLL_config(&ClkConfig.SPLL_CFG,200) == -1)
        while(1);    
    if (System_AUPLL_config(&ClkConfig.AUPLL_CFG,200) == -1)
        while(1);
    ClkConfig.MCU_Clock_Source = MCU_CLK_SEL_SPLL_CLK;
    ClkConfig.SOC_DIV  = 1;    /* This parameter is valid when MCU_Clock_Source == MCU_CLK_SEL_SPLL_CLK */
    ClkConfig.MCU_DIV  = 1;
    ClkConfig.APB0_DIV = 1;
    ClkConfig.APB1_DIV = 1;
    ClkConfig.APB2_DIV = 1;
    System_MCU_clock_Config(&ClkConfig);
#endif
    __SYSTEM_UART_CLK_SELECT_SPLL();
    __SYSTEM_SPI_MASTER1_X8_CLK_SELECT_SPLL();
}

static void display_psram_init(void)
{
		pmu_psram_power_ctrl(true);
		system_delay_us(1000);
		if(psram_init(PSRAM_CLK_SEL_AUPLL))
		{
				printf("hw_psram_init\r\n");
		}
		else
		{
				printf("hw_psram_err\r\n");
		}

		#if 1  
			__CACHE_FLUSH(CACHE);
			__CACHE_BANK_FLUSH(CACHE);
			while (__CACHE_BANK_FLUSH_DONE(CACHE) == false);
			__CACHE_WR_MODE_SET(CACHE, CACHE_WR_WRITE_THROUGH);
			__CACHE_ADDR_RANGEx_BANK_SET(CACHE, 0, 0x00000000 >> 16);
			__CACHE_ADDR_RANGEx_MASK_SET(CACHE, 0, 0x001F);
			__CACHE_ADDR_RANGEx_POL_SET(CACHE, 0, CACHE_POL_CACHABLE);
			__CACHE_ADDR_RANGEx_ENABLE(CACHE, 0);
			__CACHE_ENABLE(CACHE);
		#endif   
		 
		// test psram write & read
//		uint16_t *test_psram = (uint16_t *)PSRAM_DAC_BASE;
//		for(uint32_t i = 0; i < 100; i++)
//		{
//				test_psram[i] = 0xF800;
//		}
//		printf("\r\n");
//		for(uint32_t i=0;i<(100);i++)
//		{
//				printf("%04x",test_psram[i]);
//		}
//		printf("\r\n");
}

函数：psram

// v0.3.2
__RAM_CODE bool psram_init(enum psram_clk_sel_t clk_sel)
{
    GPIO_InitTypeDef    GPIO_Handle;
    uint32_t ref_clk;
    
    if (clk_sel >= PSRAM_CLK_SEL_MAX) {
        return false;
    }

    switch (clk_sel) {
        case PSRAM_CLK_SEL_COREH:
            __SYSTEM_OSPI_CLK_SELECT_COREH();
            ref_clk = 24000000;
            break;
        case PSRAM_CLK_SEL_SPLL:
            __SYSTEM_OSPI_CLK_SELECT_SPLL();
            ref_clk = system_get_SPLLCLK();
            break;
        case PSRAM_CLK_SEL_AUPLL:
            __SYSTEM_OSPI_CLK_SELECT_AUPLL();
            ref_clk = system_get_AUPLLCLK();
            break;
        default:
            return false;
    }
    __SYSTEM_OSPI_CLK_ENABLE();
    /* clock of AHB cache should be enabled before access psram */
    __SYSTEM_AHBC_CLK_ENABLE();

#if PSRAM_IO_GPIO == 1
    GPIO_Handle.Pin       = GPIO_PIN_12|GPIO_PIN_13;
    GPIO_Handle.Mode      = GPIO_MODE_AF_PP;
    GPIO_Handle.Pull      = GPIO_NOPULL;
    GPIO_Handle.Alternate = GPIO_FUNCTION_9;
    gpio_init(GPIOB, &GPIO_Handle);
    GPIO_Handle.Pin       = GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_5|GPIO_PIN_6;
    GPIO_Handle.Mode      = GPIO_MODE_AF_PP;
    GPIO_Handle.Pull      = GPIO_NOPULL;
    GPIO_Handle.Alternate = GPIO_FUNCTION_9;
    gpio_init(GPIOC, &GPIO_Handle);
#else
    SYSTEM->OspiPadConfig.OSPI_FuncMux = 0xFDF55FFD;
#endif

    if(psram_delay == 0xFF)
    {

        qspi_stig_cmd(PSRAM_OSPI_IF, reset_enable_cmd, QSPI_STIG_CMD_EXE, 0, NULL);
        qspi_stig_cmd(PSRAM_OSPI_IF, reset_cmd, QSPI_STIG_CMD_EXE, 0, NULL);
#if PSRAM_ENABLE_Q_MODE == 1
        psram_enter_quad();
#endif  // PSRAM_ENABLE_Q_MODE == 1
    }

    /* about 100 bytes can be transmitted during 8us when QSPI clock is 24MHz */
    ref_clk /= ((PSRAM_CLK_DIV_SEL+1) * 2);
    uint32_t bytes = ref_clk / 240000;
    uint32_t boundary_cfg = 1 << (31 - __CLZ(bytes));
    if (boundary_cfg >= 0x100) {
        boundary_cfg = 0x100;
    }
    psram_controller_init(boundary_cfg);

    if(psram_delay != 0xFF)
    {
        __QSPI_READ_CAPTURE_DELAY_SET(PSRAM_OSPI_IF, psram_delay);
    }else{
    
        /* detect read capture delay configuration */
        uint8_t delay_lower, delay_upper, index;
        *(volatile uint32_t *)(PSRAM_DAC_BASE) = 0x5a5a5a5a;
        while(__QSPI_IS_BUSY(PSRAM_OSPI_IF));

        for (index = 0; index < 16; index++) {
            while(__QSPI_IS_BUSY(PSRAM_OSPI_IF));
            __QSPI_READ_CAPTURE_DELAY_SET(PSRAM_OSPI_IF, index);
            if (*(volatile uint32_t *)(PSRAM_DAC_BASE) == 0x5a5a5a5a) {
                break;
            }
        }
        if (index == 16) {
            __SYSTEM_OSPI_CLK_DISABLE();
            __SYSTEM_AHBC_CLK_DISABLE();
            return false;
        }
        else {
            delay_lower = index;
        }
        for (; index < 16; index++) {
            while(__QSPI_IS_BUSY(PSRAM_OSPI_IF));
            __QSPI_READ_CAPTURE_DELAY_SET(PSRAM_OSPI_IF, index);
            delay_upper = index;
            if (*(volatile uint32_t *)(PSRAM_DAC_BASE) != 0x5a5a5a5a) {
                break;
            }
        }
        psram_delay = ((delay_lower + delay_upper)>>1);
        while(__QSPI_IS_BUSY(PSRAM_OSPI_IF));
        __QSPI_READ_CAPTURE_DELAY_SET(PSRAM_OSPI_IF, psram_delay);
    }
//    printf("0x%02x, %d.\r\n", 1 << (31 - __CLZ(bytes)), (delay_lower + delay_upper)/2);

    return true;
}

// v0.2.3
//__RAM_CODE 
bool psram_init(enum psram_clk_sel_t clk_sel)
{
    GPIO_InitTypeDef    GPIO_Handle;
    uint32_t ref_clk;
    
    if (clk_sel >= PSRAM_CLK_SEL_MAX) {
        return false;
    }

    switch (clk_sel) {
        case PSRAM_CLK_SEL_COREH:
            __SYSTEM_OSPI_CLK_SELECT_COREH();
            ref_clk = 24000000;
            break;
        case PSRAM_CLK_SEL_SPLL:
            __SYSTEM_OSPI_CLK_SELECT_SPLL();
            ref_clk = system_get_SPLLCLK();
            break;
        case PSRAM_CLK_SEL_AUPLL:
            __SYSTEM_OSPI_CLK_SELECT_AUPLL();
            ref_clk = system_get_AUPLLCLK();
            break;
        default:
            return false;
    }
    __SYSTEM_OSPI_CLK_ENABLE();
    /* clock of AHB cache should be enabled before access psram */
    __SYSTEM_AHBC_CLK_ENABLE();

#if PSRAM_IO_GPIO == 1
    GPIO_Handle.Pin       = GPIO_PIN_12|GPIO_PIN_13;
    GPIO_Handle.Mode      = GPIO_MODE_AF_PP;
    GPIO_Handle.Pull      = GPIO_NOPULL;
    GPIO_Handle.Alternate = GPIO_FUNCTION_9;
    gpio_init(GPIOB, &GPIO_Handle);
    GPIO_Handle.Pin       = GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_5|GPIO_PIN_6;
    GPIO_Handle.Mode      = GPIO_MODE_AF_PP;
    GPIO_Handle.Pull      = GPIO_NOPULL;
    GPIO_Handle.Alternate = GPIO_FUNCTION_9;
    gpio_init(GPIOC, &GPIO_Handle);
#else
    SYSTEM->OspiPadConfig.OSPI_InputOpenCircuit = 0xffffffff;
    SYSTEM->OspiPadConfig.OSPI_WakeupEN = 0;
    SYSTEM->OspiPadConfig.OSPI_FuncMux = 0xFDF55FFD;
#endif

    qspi_stig_cmd(PSRAM_OSPI_IF, reset_enable_cmd, QSPI_STIG_CMD_EXE, 0, NULL);
    qspi_stig_cmd(PSRAM_OSPI_IF, reset_cmd, QSPI_STIG_CMD_EXE, 0, NULL);
#if PSRAM_ENABLE_Q_MODE == 1
    psram_enter_quad();
#endif  // PSRAM_ENABLE_Q_MODE == 1

    /* about 100 bytes can be transmitted during 8us when QSPI clock is 24MHz */
    ref_clk /= ((PSRAM_CLK_DIV_SEL+1) * 2);
    uint32_t bytes = ref_clk / 240000;
    uint32_t boundary_cfg = 1 << (31 - __CLZ(bytes));
    if (boundary_cfg >= 0x100) {
        boundary_cfg = 0x100;
    }
    psram_controller_init(boundary_cfg);
    
    /* detect read capture delay configuration */
    uint8_t delay_lower, delay_upper, index;
    *(volatile uint32_t *)(PSRAM_DAC_BASE) = 0x5a5a5a5a;
    while(__QSPI_IS_BUSY(PSRAM_OSPI_IF));

    for (index = 0; index < 16; index++) {
        while(__QSPI_IS_BUSY(PSRAM_OSPI_IF));
        __QSPI_READ_CAPTURE_DELAY_SET(PSRAM_OSPI_IF, index);
        if (*(volatile uint32_t *)(PSRAM_DAC_BASE) == 0x5a5a5a5a) {
            break;
        }
    }
    if (index == 16) {
        __SYSTEM_OSPI_CLK_DISABLE();
        __SYSTEM_AHBC_CLK_DISABLE();
        return false;
    }
    else {
        delay_lower = index;
    }
    for (; index < 16; index++) {
        while(__QSPI_IS_BUSY(PSRAM_OSPI_IF));
        __QSPI_READ_CAPTURE_DELAY_SET(PSRAM_OSPI_IF, index);
        delay_upper = index;
        if (*(volatile uint32_t *)(PSRAM_DAC_BASE) != 0x5a5a5a5a) {
            break;
        }
    }
    while(__QSPI_IS_BUSY(PSRAM_OSPI_IF));
    __QSPI_READ_CAPTURE_DELAY_SET(PSRAM_OSPI_IF, (delay_lower + delay_upper)>>1);

//    printf("0x%02x, %d.\r\n", 1 << (31 - __CLZ(bytes)), (delay_lower + delay_upper)/2);

    return true;
}

问题2: v0.3.2 dma 传输数据异常 且dma_start_IT当地址指向为 (uint32_t)&hdisplay.DISPLAYx->TX_FIFO 时无法触发中断

// 初始化
{
		__SYSTEM_DMA0_CLK_ENABLE();
		/* DMA Init */
		system_dmac_request_id_config(DISPLAY_TRANS,DMA0_REQUEST_ID_2); 
		dma_handle.DMAx                       = DMA0;
		dma_handle.Channel                    = DMA_Channel1;
		dma_handle.Init.Data_Flow             = DMA_M2P_DMAC;
		dma_handle.Init.Request_ID            = 2;
		dma_handle.Init.Source_Master_Sel     = DMA_AHB_MASTER_2;
		dma_handle.Init.Desination_Master_Sel = DMA_AHB_MASTER_3;
		dma_handle.Init.Source_Inc            = DMA_ADDR_INC_INC;
		dma_handle.Init.Desination_Inc        = DMA_ADDR_INC_NO_CHANGE;
		dma_handle.Init.Source_Width          = DMA_TRANSFER_WIDTH_16;
		dma_handle.Init.Desination_Width      = DMA_TRANSFER_WIDTH_16;
		dma_handle.Init.Source_Burst_Len      = DMA_BURST_LEN_32;
		dma_handle.Init.Desination_Burst_Len  = DMA_BURST_LEN_32;
		dma_init(&dma_handle);
		
    /* panel spec: DCLK/HSYNC/VSYNC negative, DE active high */
		NVIC_ClearPendingIRQ(DMA0_IRQn);
    NVIC_EnableIRQ(DMA0_IRQn);
}
// 使用
void rgb_demo(enum_RGB_Demo_t fe_Demo)
{
		display_psram_init();
		rgb_panel_init();
		display_psram_buff = (uint16_t *)PSRAM_DAC_BASE;
		for(uint32_t i = 0; i < RGB_ROW * RGB_COL; i++)
		{
				display_psram_buff[i] = LCD_COLOR_RED;
		}
		printf("+++++%04x+++++++",display_psram_buff[53]);				
    switch(fe_Demo)
    {
        case RGB_INTERACTION_DMA:
        {
            printf("RGB demo: solid color with DMA start\r\n");
            __DISPLAY_RGB_ENABLE(hdisplay.DISPLAYx);
						uint16_t buffl[64];
						dma_start_IT(&dma_handle, (uint32_t)display_psram_buff, (uint32_t)&hdisplay.DISPLAYx->TX_FIFO, 64);
						// for(uint16_t i =0;i<64;i++)
						// {
						// 		printf("%04x",buffl[i]);
						// }
//						xTaskCreate(test_task, "test_task", 512, NULL, 2, &test_task_handle);
            break;
        }   
    }
}

extern int fputc(int c, FILE *fp);
__RAM_CODE void dma0_irq(void)
{
		void * temp = NULL;
		g_dma0_irq_cnt++;
    if (dma_get_tfr_Status(&dma_handle))
    {
        dma_clear_tfr_Status(&dma_handle);
				fputc('D',(FILE*)temp);
    }
    if (dma_get_error_Status(&dma_handle))
    {
        dma_clear_error_Status(&dma_handle);
				fputc('E',(FILE*)temp);
    }
		g_dma0_irq_cnt++;
}

当设置为：dma_start_IT(&dma_handle, (uint32_t)display_psram_buff, (uint32_t)buffl, 64);时 关掉buff1注释 打印如下

有D 打印说明进入了中断
当设置为：dma_start_IT(&dma_handle, (uint32_t)display_psram_buff, (uint32_t)&hdisplay.DISPLAYx->TX_FIFO, 64);

没有打印 D
v0.3.2 已经使用了psram当缓冲缓存数据 初始化相关文件 然后一包发送 但是使用逻辑分析仪抓取 pd12(lcd-g3) 没有波动 屏幕都不显示颜色了 持续刷屏也不显示颜色

// 完整代码

#include "fr30xx.h"
#include "user_common.h"
#include "FreeRTOS.h"
#include "task.h"
#include "driver_psram.h"

typedef struct
{
    uint32_t VerticalSignalCount;

    unsigned char *rgb_TxData;

    uint32_t vs_tvw_count;
    uint32_t vs_back_count;
    uint32_t vs_front_count;

}struct_RGB_TypeDef_t;

GPIO_InitTypeDef GPIO_Handle;
DMA_HandleTypeDef dma_handle;
DISPLAY_HandTypeDef hdisplay;
struct_RGB_TypeDef_t rgb_handle;
TaskHandle_t test_task_handle;

volatile uint32_t g_dma0_irq_cnt = 0;

#define LCD_COLOR_BLACK  0x0000
#define LCD_COLOR_WHITE  0xFFFF
#define LCD_COLOR_RED    0xF800
#define LCD_COLOR_GREEN  0x07E0
#define LCD_COLOR_BLUE   0x001F

#define RGB_VBPD    16
#define RGB_VFPD    16
#define RGB_VSPW    4
#define RGB_HBPD    8
#define RGB_HFPD    8
#define RGB_HSPW    4
#define RGB_ROW     800
#define RGB_COL     480

#define DISPLAY_PSRAM_SIZE					(RGB_ROW*RGB_COL*2)

#define LOAD_ORIG_FRAMEBUFFER       (void *)(PSRAM_DAC_BASE+ 60 + DISPLAY_PSRAM_SIZE)
#define LOAD_LEFT_FRAMEBUFFER       (void *)(PSRAM_DAC_BASE+ 60 + DISPLAY_PSRAM_SIZE*2)
#define LOAD_RIGHT_FRAMEBUFFER      (void *)(PSRAM_DAC_BASE+ 60 + DISPLAY_PSRAM_SIZE*3)

volatile uint8_t refr_wait_sign = 0;

static uint16_t *display_psram_buff; 

static void display_psram_init(void)
{
		pmu_psram_power_ctrl(true);
		system_delay_us(1000);
		if(psram_init(PSRAM_CLK_SEL_AUPLL))
		{
				printf("hw_psram_init\r\n");
		}
		else
		{
				printf("hw_psram_err\r\n");
		}

		#if 1  
			__CACHE_FLUSH(CACHE);
			__CACHE_BANK_FLUSH(CACHE);
			while (__CACHE_BANK_FLUSH_DONE(CACHE) == false);
			__CACHE_WR_MODE_SET(CACHE, CACHE_WR_WRITE_THROUGH);
			__CACHE_ADDR_RANGEx_BANK_SET(CACHE, 0, 0x00000000 >> 16);
			__CACHE_ADDR_RANGEx_MASK_SET(CACHE, 0, 0x001F);
			__CACHE_ADDR_RANGEx_POL_SET(CACHE, 0, CACHE_POL_CACHABLE);
			__CACHE_ADDR_RANGEx_ENABLE(CACHE, 0);
			__CACHE_ENABLE(CACHE);
		#endif   
		 
		// test psram write & read
//		uint16_t *test_psram = (uint16_t *)PSRAM_DAC_BASE;
//		for(uint32_t i = 0; i < 100; i++)
//		{
//				test_psram[i] = 0xF800;
//		}
//		printf("\r\n");
//		for(uint32_t i=0;i<(100);i++)
//		{
//				printf("%04x",test_psram[i]);
//		}
//		printf("\r\n");
}

static void test_task(void *arg)
{
    while(1) {
//        printf("dma irq cnt=%d \r\n", g_dma0_irq_cnt);
				display_rgb_write_data(&hdisplay,display_psram_buff,RGB_ROW * RGB_COL);
				vTaskDelay(1000);
    }
}

static void rgb_panel_init(void)
{
		/* init display CLOCK */  
    __SYSTEM_DISPLAY_CLK_ENABLE();
//    __SYSTEM_DISPLAY_CLK_SELECT_D48M();
		__SYSTEM_DISPLAY_CLK_SELECT_SPLL();
    __SYSTEM_GPIOB_CLK_ENABLE();
    __SYSTEM_GPIOD_CLK_ENABLE();
    __SYSTEM_DMA0_CLK_ENABLE();
    __SYSTEM_TIMER0_CLK_ENABLE();
		
		printf("display clock:%d\r\n", system_get_peripheral_clock(PER_CLK_DISPLAY));
		
		/* RGB io init */
		GPIO_Handle.Alternate = GPIO_FUNCTION_8;
    GPIO_Handle.Mode      = GPIO_MODE_AF_PP;
    GPIO_Handle.Pin       = 0xF00;
    GPIO_Handle.Pull      = GPIO_PULLUP;
    gpio_init(GPIOB, &GPIO_Handle);

    GPIO_Handle.Alternate = GPIO_FUNCTION_8;
    GPIO_Handle.Mode      = GPIO_MODE_AF_PP;
    GPIO_Handle.Pin       = 0xFFFF;
    GPIO_Handle.Pull      = GPIO_PULLUP;
    gpio_init(GPIOD, &GPIO_Handle);

    GPIO_Handle.Alternate = GPIO_FUNCTION_0;
    GPIO_Handle.Mode      = GPIO_MODE_OUTPUT_PP;
    GPIO_Handle.Pin       = GPIO_PIN_7;
    GPIO_Handle.Pull      = GPIO_PULLUP;
    gpio_init(GPIOB, &GPIO_Handle);
    gpio_write_pin(GPIOB, GPIO_PIN_7, GPIO_PIN_SET);

		/* RGB Interaction Init */ 
		hdisplay.DISPLAYx = DISPLAY;
		hdisplay.RGB_Init.RGB_OUT_FORMAT_SELECT = RGB565_OUT;
		hdisplay.RGB_Init.RGB_IN_FORMAT_SELECT = RGB565_IN;
		hdisplay.Interface_Select = DISPLAY_INTERFACE_RGB;
		/* 
			 RGB Timing Init
		*/         
		hdisplay.RGB_Init.HBP = RGB_HBPD;
		hdisplay.RGB_Init.HFP = RGB_HFPD; 
		hdisplay.RGB_Init.VBP = RGB_VBPD;
		hdisplay.RGB_Init.VFP = RGB_VFPD;  
		hdisplay.RGB_Init.HSPW = RGB_HSPW; 
		hdisplay.RGB_Init.VSPW = RGB_VSPW;   
		hdisplay.RGB_Init.HRES = RGB_ROW;  
		hdisplay.RGB_Init.VRES = RGB_COL;
		display_init(&hdisplay);
		
		/* RGB_CLK =  (PER_CLK_RGB / 5*2) */              
    __DISPLAY_RGB_SET_PIXEL_CLK_DIV(hdisplay.DISPLAYx,8);  
		
		/* DMA Init */
		system_dmac_request_id_config(DISPLAY_TRANS,DMA0_REQUEST_ID_2); 
		dma_handle.DMAx                       = DMA0;
		dma_handle.Channel                    = DMA_Channel1;
		dma_handle.Init.Data_Flow             = DMA_M2P_DMAC;
		dma_handle.Init.Request_ID            = 2;
		dma_handle.Init.Source_Master_Sel     = DMA_AHB_MASTER_2;
		dma_handle.Init.Desination_Master_Sel = DMA_AHB_MASTER_3;
		dma_handle.Init.Source_Inc            = DMA_ADDR_INC_INC;
		dma_handle.Init.Desination_Inc        = DMA_ADDR_INC_NO_CHANGE;
		dma_handle.Init.Source_Width          = DMA_TRANSFER_WIDTH_16;
		dma_handle.Init.Desination_Width      = DMA_TRANSFER_WIDTH_16;
		dma_handle.Init.Source_Burst_Len      = DMA_BURST_LEN_32;
		dma_handle.Init.Desination_Burst_Len  = DMA_BURST_LEN_32;
		dma_init(&dma_handle);
		
    /* panel spec: DCLK/HSYNC/VSYNC negative, DE active high */
		NVIC_ClearPendingIRQ(DMA0_IRQn);
    NVIC_EnableIRQ(DMA0_IRQn);
}

/************************************************************************************
 * @fn      rgb_demo
 *
 * @brief   rgb demo
 *
 * @param   fe_Demo: demo select. 

 */
void rgb_demo(enum_RGB_Demo_t fe_Demo)
{
		display_psram_init();
		rgb_panel_init();
		display_psram_buff = (uint16_t *)PSRAM_DAC_BASE;
		for(uint32_t i = 0; i < RGB_ROW * RGB_COL; i++)
		{
				display_psram_buff[i] = LCD_COLOR_RED;
		}
		printf("+++++%04x+++++++",display_psram_buff[53]);				
    switch(fe_Demo)
    {
        case RGB_INTERACTION:
        {
						printf("RGB demo: solid color start\r\n");
            __DISPLAY_RGB_ENABLE(hdisplay.DISPLAYx);
//            dma_start(&dma_handle,(uint32_t)(display_psram_buff),(uint32_t)&hdisplay.DISPLAYx->TX_FIFO, RGB_ROW * RGB_COL);
//						while(!dma_get_tfr_Status(&dma_handle));
//            dma_clear_tfr_Status(&dma_handle);
						xTaskCreate(test_task, "test_task", 512, NULL, 2, &test_task_handle);
						break;
        }
        
        case RGB_INTERACTION_DMA:
        {
            printf("RGB demo: solid color with DMA start\r\n");
            __DISPLAY_RGB_ENABLE(hdisplay.DISPLAYx);
						uint16_t buffl[64];
						dma_start_IT(&dma_handle, (uint32_t)display_psram_buff, (uint32_t)&hdisplay.DISPLAYx->TX_FIFO, 64);
//						for(uint16_t i =0;i<64;i++)
//						{
//								printf("%04x",buffl[i]);
//						}
//						xTaskCreate(test_task, "test_task", 512, NULL, 2, &test_task_handle);
            break;
        }   
    }
}

extern int fputc(int c, FILE *fp);
__RAM_CODE void dma0_irq(void)
{
		void * temp = NULL;
		g_dma0_irq_cnt++;
    if (dma_get_tfr_Status(&dma_handle))
    {
        dma_clear_tfr_Status(&dma_handle);
				fputc('D',(FILE*)temp);
//        if(refr_wait_sign)
//        {
//            __DISPLAY_RGB_DISABLE(hdisplay.DISPLAYx);
//        }
//        else
//        {
//            __DISPLAY_RGB_ENABLE(hdisplay.DISPLAYx);
//            dma_start_IT(&dma_handle,(uint32_t)display_psram_buff,(uint32_t)&hdisplay.DISPLAYx->TX_FIFO, RGB_ROW * RGB_COL);
//        }
    }
    if (dma_get_error_Status(&dma_handle))
    {
        dma_clear_error_Status(&dma_handle);
				fputc('E',(FILE*)temp);
    }
		g_dma0_irq_cnt++;
}